Very-Large Scale Integrated (VLSI) circuits and Ultra-Large Scale Integrated (VLSI) circuits include interconnect structures having electrically conductive wires that connect devices in different levels of a semiconductor chip to each other. The conductive interconnects include metals, such as, for example, aluminum or copper, insulated by dielectric materials. Trends in the semiconductor industry have led to reduced gate length and chip size, resulting in smaller interconnect structures. As the interconnect structures decrease in size, overlay error between elements in the interconnect structure caused by misalignment during a lithography process, and the resulting reliability issues, have become areas of concern to semiconductor manufacturers.
Processing to form metal interconnects or vias that are fully aligned to a first metallization level (M1) and a second metallization level (M2) on the first metallization level has been attempted. The fully aligned metal interconnects are referred to herein as fully aligned vias (FAVs). In connection with FAV processing, topography from an underlying metal is used to define a via in a non-self-aligned via (non-SAV) direction. Using the topography from an underlying metal to define a via in a non-SAV direction can be very challenging where the underlying level has certain structures that may be difficult to recess.